The present invention relates to semiconductor devices and, more particularly, to a semiconductor device which generates a clock signal that is synchronized with a reference signal, like a horizontal synchronizing signal in a video signal.
In recent years, video signal processing in digital has been advancing, and semiconductor devices for synchronizing a clock that is employed in the video signal processing with reference signal like a horizontal synchronizing signal in a video signal are utilized in the video signal processing.
Hereinafter, these conventional semiconductor devices will be described.
A first prior art is described with reference to FIGS. 9, 11, 12 and 13.
FIG. 9 is a circuit diagram illustrating a prior art semiconductor device.
In FIG. 9, a reference signal input terminal 101 receives a reference signal. A phase comparator 102 compares an output of a dividing circuit 105 with the reference signal to generate a difference signal, and outputs the difference signal as a phase difference output. A low-pass filter (hereinafter, referred to as LPF) 103 converts the phase difference signal that is outputted from the phase comparator 102 into a voltage, and outputs an obtained voltage as a control voltage for controlling a VCO 104. The VCO 104 is controlled by the control voltage that is outputted from the LPF 103, and converts a clock frequency on the basis of the phase difference to output a synchronous clock (sync clock). The dividing circuit 105 divides the sync clock that is outputted from the VCO 104, and outputs the obtained signal to the phase comparator 102 as a comparison signal. The sync clock that is outputted from the VCO 104 is outputted to the outside from a clock output terminal 106.
FIG. 11 is a circuit diagram illustrating the phase comparator 102 shown in FIG. 9. Reference numeral 110 denotes a target signal input terminal. Numeral 111 denotes a comparison signal input terminal. Numeral 112 denotes a phase difference output terminal. FIGS. 12(a) to 12(c) are timing charts for explaining the phase comparator 102 shown in FIG. 11. FIG. 12(a) shows a signal waveform of a target signal that is inputted to the target signal input terminal 110. FIG. 12(b) shows a signal waveform of a comparison signal that is inputted to the comparison signal input terminal 111. FIG. 12(c) shows a signal waveform of a phase difference output that is outputted from the phase difference output terminal 112.
FIG. 13 is a circuit diagram illustrating the LPF 103 shown in FIG. 9. Numeral 120 denotes a phase difference input terminal. Numerals 121 and 122 denote resistors. Numerals 123 and 124 denote capacitors. Numeral 125 denotes a control voltage output terminal. The LPF 103 constituted as described above converts the phase difference signal which is outputted from the phase comparator 102 and is inputted to the phase difference input terminal 120 into a voltage, and outputs the obtained voltage from the control voltage output terminal 125 as a control voltage for controlling the VCO 104.
Next, the operation of the first prior art semiconductor device will be described.
The reference signal that is inputted through the reference signal input terminal 101 is inputted to the phase comparator 102 as a target signal. A clock that is synchronized with the reference signal is generated by the VCO 104 and is outputted to the dividing circuit 105 as well as to the outside through the clock output terminal 106.
The sync clock inputted to the dividing circuit 105 is frequency-divided by the dividing circuit 105, and the divided clock is inputted to the phase comparator 102 as a comparison signal. At this time, the dividing circuit 105 divides the sync clock so that the frequency of the reference signal coincides with the frequency of the comparison signal.
The phase comparator 102 compares the comparison signal with the reference signal as the target signal to generate a difference signal, and outputs the difference signal as a phase difference output.
As the phase comparator 102, a phase comparator shown in FIG. 11 is commonly used. The reference signal is inputted as a target signal to the target signal input terminal 110, and the signal obtained by the dividing circuit 105 is inputted to the comparison signal input terminal 111 as a comparison signal. When a change point of the target signal is located before a change point of the comparison signal as shown in FIG. 12, an H pulse corresponding to the phase difference is outputted to the phase difference output terminal 112 as a phase difference output. When the change point of the target signal is located behind the change point of the comparison signal, an L pulse corresponding to the phase difference is outputted to the phase difference output terminal 112 as a phase difference output.
Then, the phase difference output that is a pulse outputted from the phase comparator 102 is inputted to the LPF 103, and is converted into a voltage for controlling the VCO 104 to be inputted to the VCO 104 as a control voltage.
Then, the VCO 104 is controlled by the control voltage outputted from the LPF 103, and changes the frequency of the clock outputted from the VCO 104 by the phase difference.
By repeating the above-mentioned operation until the phase comparator 102 comes to detect no phase difference between the signal obtained by the dividing circuit 105 and the reference signal inputted through the reference signal input terminal 101, a clock signal that is synchronized with the reference signal which is inputted through the reference signal input terminal 101 can be generated, and a clock signal synchronized with the reference signal can be outputted from the clock output terminal 106.
A second prior art will be described with reference to FIG. 10.
FIG. 10 is a circuit diagram illustrating a prior art semiconductor device for synchronizing a clock with a reference signal. Numeral 131 denotes a clock input terminal. Numerals 132 to 139 denote buffers. Numeral 140 denotes a reference signal input terminal. Numeral 141 denotes a selector. Numeral 142 denotes a sync clock output terminal.
Next, the operation of the prior art semiconductor device for synchronizing a clock with a reference signal is described.
A clock having the same frequency as that of a desired clock is inputted to the clock input terminal 131. The inputted clock is delayed by the buffers 132 to 139, and clocks which are slightly shifted in phase with each other are outputted from the respective buffers.
The selector 141 selects a clock having a phase closest to that of the reference signal that is inputted through the reference signal input terminal 140, from the clocks having the various phases which are outputted from the respective buffers 132 to 139, and outputs the selected clock as a sync clock from the sync clock output terminal 142.
As described above, in this second prior art, the selector 141 selects a clock having a phase closest to that of the reference signal, thereby obtaining a clock synchronized with the reference signal.
However, in the first prior art, the sync clock is generated by repeating the phase comparison between the reference signal inputted through the reference signal input terminal 101 and a clock signal to be synchronized with the reference signal by means of the phase comparator 102. Therefore, when the phase of the reference signal varies abruptly, it is hard for the sync clock to follow the reference signal. Further, in order to keep the frequency of the sync clock constant, it is required to keep the control voltage of the VCO 104 at a constant value after clock synchronization with the reference signal is performed and before the next reference signal is inputted. However, when the interval between the reference signals is large, the oscillated frequency of the VCO 104 varies due to interferences such as supply voltage noises occurring in the control voltage for the VCO 104, thereby making it difficult to keep the synchronization.
On the other hand, in the second prior art, delayed clocks are generated by the buffers 132 to 139 and one of the clocks which are outputted from the buffers 132 to 139 and have respective phases is selected on the basis of the reference signal to be outputted as a sync signal, whereby the signal can follow even an abrupt phase change in the reference signal, while when the voltages of the buffers 132 to 139 or the temperature vary due to interferences, delays of clocks by the buffers 132 to 139 would vary. Because the delays of the clocks by the buffers 132 to 139 should vary due to variations in the voltage or the temperature, even when the selector 141 selects a clock having a phase that is the closest to that of the inputted reference signal, a sync clock with sufficient accuracy cannot be obtained. Particularly, an LSI which is a system including a plurality of devices such as logic circuits which have various functions on one chip is easily affected by interferences from other devices, whereby sync clocks with sufficient accuracy cannot be obtained.
Further, in order to obtain sufficient accuracy, the delays of the buffers that perform delaying need be made smaller, which increases the number of stages. However, when the delays of the buffers that perform delaying are made smaller and the number of stages is increased, the circuit scales of the buffers and the selector are adversely increased.
The present invention has for its object to provide a semiconductor device which can generate a clock signal accurately synchronized with a reference signal even when the phase of the reference signal abruptly changes, even when the phase interval between the reference signals is large, or even when interferences of the voltage or the temperature occur, and which is particularly useful when a high-speed clock is to be synchronized with a reference clock.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a 1st aspect of the present invention, there is provided a semiconductor device comprising: an external clock input means for receiving an external clock that is a clock to be synchronized; N stages of delay elements each delaying the external clock by 1/N clock (N is an integer that is two or larger); a phase comparison means for comparing a phase of a clock that has been delayed by the N stages of the delay elements with a phase of the external clock one clock late, and detecting a phase difference; a control means for controlling respective delays of the delay elements on the basis of the phase difference detected by the phase comparison means; a reference signal input terminal for receiving a reference signal; and a selection means for selecting one of delayed clocks which are generated by the N stages of the delay elements, respectively, and shifted in phase with each other by 1/N clock, on the basis of the reference signal, and outputting the selected clock as a synchronous clock. Therefore, frequencies of the clocks which are outputted from the respective delay elements can be kept constant without being affected by interferences of the voltage or the temperature. Consequently, a synchronous clock having higher synchronization accuracy can be always obtained.
According to a 2nd aspect of the present invention, in the semiconductor device of the 1st aspect, the selection means selects a delayed clock having a change point which is behind a change point of the reference signal and is closest thereto, among the delayed clocks which are generated by the N stages of the delay elements, respectively, and are shifted in phase with each other by 1/N clock. Therefore, even when the interval between the reference signals is large or even when the reference signal abruptly changes, a clock accurately synchronized with the reference signal can be obtained.
According to a 3rd aspect of the present invention, in the semiconductor device of the 1st aspect, the selection means selects a delayed clock having a change point that is before a change point of the reference signal and is the closest thereto, among the delayed clocks which are generated by the N stages of the delay elements, respectively, and are shifted in phases with each other by 1/N clock. Therefore, even when the interval between the reference signals is large or even when the reference signal abruptly changes, clocks which are accurately synchronized with the reference signal can be obtained.
According to a 4th aspect of the present invention, in the semiconductor device of any of the 1st to 3rd aspect, the selection means comprises: a latch circuit for latching each of the delayed clocks which are generated by the N stages of the delay elements, respectively, and are shifted in phase with each other by 1/N clock, in accordance with the reference signal; a control circuit for deciding a timing of the clock selection; and a multiplexer for receiving outputs from the latch circuit, and selecting one of the delayed clocks which are shifted in phase with each other by 1/N clock, at the decided timing that is outputted by the control circuit. Therefore, the switching timings of the delayed clocks which are outputted from the delay elements are fixed, thereby facilitating the use of synchronous clocks in systems that employ thus generated synchronous clocks.
According to a 5th aspect of the present invention, the semiconductor device of any of the 1st to 4th aspect further includes: a clock stop means for temporarily stopping the delayed clocks which are generated by the N stages of the delay elements, respectively, and are shifted in phase with each other by 1/N clock, at the clock selection by the selection means. Therefore, occurrence of a clock having a pulse length that is shorter than that of the normal clock can be prevented at the clock switching, whereby improper operations in the systems that employ the generated sync clocks can be prevented.
According to a 6th aspect of the present invention, the semiconductor device of any of the 1st to 4th aspect further includes: a pre-delay detection means for detecting whether or not the delays of the N stages of the delay elements are smaller than a predetermined value, and outputting an obtained result to the control means, and the control means controls the N stages of the delay elements on the basis of the output from the pre-delay detection means so that the delays have the predetermined value. Therefore, the comparison in the phase comparison means between the phase of the non-delay clock and the phase of the external clock one clock late can be prevented, whereby the delayed clocks which are shifted in phase with each other by 1/N clock can be always generated.
According to a 7th aspect of the present invention, in the semiconductor device of the 6th aspect, the pre-delay detection means includes: a dividing circuit for dividing the external clock; a first latch circuit comprising latch circuits of two or more stages for receiving an output from the dividing circuit and delaying the output in clock units; delay elements of (N+1) stages or more which receive the output from the dividing circuit and have the same delays as those of the N stages of the delay elements; a second latch circuit for latching an output from the delay elements of (N+1) stages or more, in accordance with the external clock; and a comparator for comparing an output from the first latch circuit with an output from the second latch circuit. Therefore, variations in the delays of the delay elements are always monitored to quickly detect that the delays of the delay elements are slightly varied by the interferences, whereby the delays of the delay elements can be controlled to the predetermined value. Consequently a clock that is accurately synchronized with the reference signal can be generated.
According to an 8th aspect of the present invention, the semiconductor device of any of the 1st to 4th aspect further includes: a post-delay detection means for detecting whether the delays of the N stages of the delay elements are larger than a predetermined value, and outputting an obtained result to the control means, and the control means controls the N stages of the delay elements on the basis of the output from the post-delay detection means so that the delays have a predetermined value. Therefore, the comparison by the phase comparison means between the phase of a delayed clock that has been delayed by two clocks or more and the phase of the external clock one clock late can be prevented, whereby the delayed clocks which are shifted in phase with each other by 1/N clock can be always generated.
According to a 9th aspect of the present invention, in the semiconductor device of the 8th aspect, the post-delay detection means includes: a dividing circuit for dividing the external clock; a third latch circuit for receiving an output from the dividing circuit and delaying the output by one clock; delay elements of (Nxe2x88x921) stages or less which receive the output from the dividing circuit and have the same delays as those of the N stages of the delay elements; a fourth latch circuit for latching an output from the delay elements of (Nxe2x88x921) stages or less, in accordance with the external clock; and a comparator for comparing an output from the third latch circuit with an output from the fourth latch circuit. Therefore, variations in the delays of delay elements are always monitored to quickly detect that the delays of the delay elements are greatly varied due to the interferences, whereby the delays of the delay elements are controlled to a predetermined value. Consequently, a clock that is accurately synchronized with the reference signal can be generated.